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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM6226BB/D
128K x 8 Bit Static Random Access Memory
The MCM6226BB is a 1,048,576 bit static random access memory organized as 131,072 words of 8 bits. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6226BB is equipped with both chip enable (E1 and E2) and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. The MCM6226BB is available in 300 mil and 400 mil, 32 lead surface-mount SOJ packages. * * * * * * Single 5 V 10% Power Supply Fast Access Times: 15/17/20/25/35 ns Equal Address and Chip Enable Access Times All Inputs and Outputs are TTL Compatible Three State Outputs Low Power Operation: 190/180/165/150/130 mA Maximum, Active AC BLOCK DIAGRAM
MCM6226BB
XJ PACKAGE 400 MIL SOJ CASE 857A-02
EJ PACKAGE 300 MIL SOJ CASE 857-02
PIN ASSIGNMENT
NC A A A A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A E2 W A A A A G A E1 DQ DQ DQ DQ DQ
A A A A A A A A A ROW DECODER MEMORY MATRIX 512 ROWS x 2048 COLUMNS
A A A A A A DQ DQ DQ VSS
DQ DQ
INPUT DATA CONTROL
COLUMN I/O COLUMN DECODER
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable E1, E2 . . . . . . . . . . . . . . . . Chip Enables DQ . . . . . . . . . . . . . Data Inputs/Outputs NC . . . . . . . . . . . . . . . . . . No Connection VCC . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . Ground
E1 E2 W G
A
A
A
A
A
A
A
A
REV 2 10/31/96
(c) Motorola, Inc. 1996 MOTOROLA FAST SRAM
MCM6226BB 1
TRUTH TABLE
E1 H X L L L E2 X L H H H G X X H L X W X X H H L Mode Not Selected Not Selected Output Disabled Read Write I/O Pin High-Z High-Z High-Z Dout Din Cycle -- -- -- Read Write Current ISB1, ISB2 ISB1, ISB2 ICCA ICCA ICCA
H = High, L = Low, X = Don't Care
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to 7.0 - 0.5 to VCC + 0.5 20 1.0 - 10 to + 85 0 to + 70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
Storage Temperature Tstg - 55 to + 150 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns). ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width 20 ns). Symbol VCC VIH VIL Min 4.5 2.2 - 0.5* Max 5.5 VCC + 0.3** 0.8 Unit V V V
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E* = VIH, Vout = 0 to VCC) AC Active Supply Current (Iout = 0 mA, all inputs = VIL or VIH, VIL = 0, VIH 3 V, cycle time tAVAV min, VCC = max) MCM6226BB-15: tAVAV = 15 ns MCM6226BB-17: tAVAV = 17 ns MCM6226BB-20: tAVAV = 20 ns MCM6226BB-25: tAVAV = 25 ns MCM6226BB-35: tAVAV = 35 ns MCM6226BB-15: tAVAV = 15 ns MCM6226BB-17: tAVAV = 17 ns MCM6226BB-20: tAVAV = 20 ns MCM6226BB-25: tAVAV = 25 ns MCM6226BB-35: tAVAV = 35 ns Symbol Ilkg(I) Ilkg(O) ICCA Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.4 Max 1 1 195 180 165 150 130 45 40 35 30 25 5 0.4 -- Unit A A mA
AC Standby Current (VCC = max, E* = VIH, f = fmax)
ISB1
mA
CMOS Standby Current (E* VCC - 0.2 V, Vin VSS + 0.2 V or VCC - 0.2 V, VCC = max, f = 0 MHz) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) *E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.
ISB2 VOL VOH
mA V V
MCM6226BB 2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Characteristic Input Capacitance I/O Capacitance All Inputs Except Clocks and DQs E1, E2, G, and W DQ Symbol Cin Cck CI/O Typ 4 5 5 Max 6 8 8 Unit pF pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1a
READ CYCLE TIMING (See Notes 1, 2, and 3)
6226BB-15 Parameter Read Cycle Time Address Access Time Enable Access Time Output Enable Access Time Output Hold from Address Change Enable Low to Output Active Output Enable Low to Output Active Enable High to Output High-Z Output Enable High to Output High-Z Symbol tAVAV tAVQV tELQV tGLQV tAXQX tELQX tGLQX tEHQZ tGHQZ Min 15 -- -- -- 3 5 0 -- -- Max -- 15 15 6 -- -- -- 6 6 6226BB-17 Min 17 -- -- -- 3 5 0 -- -- Max -- 17 17 7 -- -- -- 7 7 6226BB-20 Min 20 -- -- -- 3 5 0 -- -- Max -- 20 20 7 -- -- -- 7 7 6226BB-25 Min 25 -- -- -- 3 5 0 -- -- Max -- 25 25 8 -- -- -- 8 8 6226BB-35 Min 35 -- -- -- 3 5 0 -- -- Max -- 35 35 8 -- -- -- 8 8 Unit ns ns ns ns ns ns ns ns ns 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 5 Notes 4
NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1. 4. All timings are referenced from the last valid address to the first transitioning address. 5. Addresses valid prior to or coincident with E going low. 6. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device and from device to device. 7. Transition is measured 500 mV from steady-state voltage with load of Figure 1b. 8. This parameter is sampled and not 100% tested. 9. Device is continuously selected (E VIL, G VIL).
TIMING LIMITS
+5 V OUTPUT Z0 = 50 RL = 50 VL = 1.5 V OUTPUT 255 5 pF 480 The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
(a)
(b)
Figure 1. AC Test Loads
MOTOROLA FAST SRAM
MCM6226BB 3
READ CYCLE 1 (See Notes 1, 2, 3, and 9)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
READ CYCLE 2 (See Notes 3 and 5)
tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tELQX G (OUTPUT ENABLE) tGLQV tGLQX Q (DATA OUT) HIGH-Z tAVQV tELICCH ICC SUPPLY CURRENT ISB tEHICCL DATA VALID tGHQZ tEHQZ
MCM6226BB 4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1, 2, 3, and 4)
6226BB-15 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Data Valid to End of Write Data Hold TIme Write Low to Data High-Z Write High to Output Active Write Recovery Time Symbol tAVAV tAVWL tAVWH tWLWH, tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 15 0 12 12 7 0 -- 5 0 Max -- -- -- -- -- -- 6 -- -- 6226BB-17 Min 17 0 14 14 8 0 -- 5 0 Max -- -- -- -- -- -- 7 -- -- 6226BB-20 Min 20 0 15 15 9 0 -- 5 0 Max -- -- -- -- -- -- 7 -- -- 6226BB-25 Min 25 0 17 17 10 0 -- 5 0 Max -- -- -- -- -- -- 8 -- -- 6226BB-35 Min 35 0 20 20 11 0 -- 5 0 Max -- -- -- -- -- -- 8 -- -- Unit ns ns ns ns ns ns ns ns ns 6, 7, 8 6, 7, 8 Notes 5
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1. 4. If G goes low coincident with or after W goes low, the output will remain in a high-impedance state. 5. All timings are referenced from the last valid address to the first transitioning address. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 1b. 7. This parameter is sampled and not 100% tested. 8. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
WRITE CYCLE 1 (W Controlled See Notes 1, 2, 3, and 4)
tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE)
tWLWH tWLEH
tWHAX
W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tDVWH DATA VALID tWHQX tWHDX
MOTOROLA FAST SRAM
MCM6226BB 5
WRITE CYCLE 2 (E Controlled, See Notes 1, 2, 3, and 4)
6226BB-15 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Enable to End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Recovery Time Symbol tAVAV tAVEL tAVEH tELEH, tELWH tWLEH tDVEH tEHDX tEHAX Min 15 0 12 12 12 7 0 0 Max -- -- -- -- -- -- -- -- 6226BB-17 Min 17 0 14 14 14 8 0 0 Max -- -- -- -- -- -- -- -- 6226BB-20 Min 20 0 15 15 15 9 0 0 Max -- -- -- -- -- -- -- -- 6226BB-25 Min 25 0 17 17 17 10 0 0 Max -- -- -- -- -- -- -- -- 6226BB-35 Min 35 0 20 20 20 11 0 0 Max -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns 6, 7 Notes 5
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1. 4. If G goes low coincident with or after W goes low, the output will remain in a high-impedance state. 5. All timings are referenced from the last valid address to the first transitioning address. 6. If E goes low coincident with or after W goes low, the output will remain in a high-impedance state. 7. If E goes high coincident with or before W goes high, the output will remain in a high-impedance state.
WRITE CYCLE 2 (E Controlled See Notes 1, 2, 3, and 4)
tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX Q (DATA OUT) HIGH-Z tELWH tEHAX
ORDERING INFORMATION
(Order by Full Part Number) MCM 6226BB XX
Motorola Memory Prefix Part Number
XX
XX
Shipping Method (R2 = Tape and Reel, Blank = Rails) Speed (15 = 15 ns, 17 = 17 ns, 20 = 20 ns, 25 = 25 ns, 35 = 35 ns) Package (XJ = 400 mil SOJ, EJ = 300 mil SOJ)
Full Part Numbers -- MCM6226BBXJ15 MCM6226BBXJ17 MCM6226BBXJ20 MCM6226BBXJ25 MCM6226BBXJ35
MCM6226BBXJ15R2 MCM6226BBXJ17R2 MCM6226BBXJ20R2 MCM6226BBXJ25R2 MCM6226BBXJ35R2
MCM6226BBEJ15 MCM6226BBEJ17 MCM6226BBEJ20 MCM6226BBEJ25 MCM6226BBEJ35
MCM6226BBEJ15R2 MCM6226BBEJ17R2 MCM6226BBEJ20R2 MCM6226BBEJ25R2 MCM6226BBEJ35R2
MCM6226BB 6
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
32 LEAD 400 MIL SOJ CASE 857A-02
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TO BE DETERMINED AT PLANE -T-. 4. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION A & B INCLUDE MOLD MISMATCH AND ARE DETERMINED AT THE PARTING LINE. DIM A B C D E F G K L N P R S MILLIMETERS MIN MAX 20.83 21.08 10.03 10.29 3.75 3.26 0.50 0.41 2.48 2.24 0.81 0.67 1.27 BSC 1.14 0.89 0.64 BSC 1.14 0.76 11.30 11.05 9.52 9.27 1.01 0.77 INCHES MIN MAX 0.820 0.830 0.395 0.405 0.128 0.148 0.016 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.035 0.045 0.025 BSC 0.030 0.045 0.435 0.445 0.365 0.375 0.030 0.040
32
17
F N
32 PL
0.17 (0.007)
DETAIL Z
S
TB
S
A
S
1
16
0.17 (0.007) -AL G
S
D 32 PL T BS A
S
S
NOTE 3
P 0.17 (0.007) -B0.10 (0.004)
TA
S
B
S
E R 0.25 (0.010)
S
C
K
DETAIL Z
-T-
SEATING PLANE
S RADIUS TA
S
B
S
NOTE 3
MOTOROLA FAST SRAM
MCM6226BB 7
32 LEAD 300 MIL SOJ CASE 857-02
F 32 PL 0.17 (0.007)
32 1 17
S
A
S
M
NOTE 4
16
-A- L G -X-
DETAIL Z NOTE 3
D 32 PL 0.17 (0.007) P 0.17 (0.007) S B -B-
NOTE 5 S S
A
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DATUM PLANE -X- LOCATED AT TOP OF MOLD PARTING LINE AND COINCIDENT WITH TOP OF LEAD, WHERE LEAD EXITS BODY. 4. TO BE DETERMINED AT PLANE -X-. 5. TO BE DETERMINED AT PLANE -T-. 6. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 7. 857-01 IS OBSOLETE, NEW STANDARD 857-02. DIM A B C D E F G K L N P R S MILLIMETERS MIN MAX 20.83 21.08 7.74 7.50 3.75 3.26 0.50 0.41 2.48 2.24 0.81 0.67 1.27 BSC 1.14 0.89 0.64 BSC 1.14 0.76 8.64 8.38 6.86 6.60 1.01 0.77 INCHES MIN MAX 0.820 0.830 0.295 0.305 0.128 0.148 0.016 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.035 0.045 0.025 BSC 0.030 0.045 0.330 0.340 0.260 0.270 0.030 0.040
EC R 0.25 (0.010)
S
0.10 (0.004)
K
-T-
SEATING PLANE
S RADIUS B
S NOTE 5
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MCM6226BB 8
MOTOROLA MCM6226BB/D FAST SRAM

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